Publications

Deliverables

D1.1 Requirements and concept of the diagnostic model
D1.2 Definition of the diagnostic model
D1.3 Status on the reasoning engines and dynamic techniques
D1.4 Report on reasoning engines and dynamic techniques
D2.1 Transaction-level diagnosis
D2.2a Status on implementation-level diagnosis
D2.2b Tools for implementation-level diagnosis
D2.3a Status on post-silicon and in-situ diagnosis
D2.3b Tools for post-silicon and in-situ diagnosis
D3.1 Transaction-level correction
D3.2a Status on implementation-level correction
D3.2b Tools for transaction-level correction
D3.3a Status on post-silicon and in-situ repair
D3.3b Tools for post-silicon and in-situ repair
D4.1 Definition of end-user requirements
D4.2 Definition of the DIAMOND platform
D4.3 Validation of diagnosis and debug prototypes
D4.4 Final evaluation of the DIAMOND flow
D5.1 DIAMOND website
D5.2 Project flyer
D5.3 40 articles in international journals and proceedings
D5.4 Dissemination workshops
D5.5 Technology Exploitation Plan
D5.6 Dissemination report (to be reported also on the website)
D6.1 Periodic Activity Reports
D6.2 Project Final report

Publications 2010

Hanno Hantson, Jaan Raik, Maksim Jenihhin, Anton Chepurov, Raimund Ubar, Giuseppe di Guglielmo, Franco Fummi, "Mutation analysis with high-level decision diagrams", 11th Latin American Test Workshop (LATW), Punta del Este, Uruguay, March 28-31, 2010.

Dimitar Nikolov, Urban Ingelsson,Virendra Singh and Erik Larsson, "On-line techniques to adjust and optimize checkpointing frequency", IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010), Bangalore, India, January 7-8, 2010.

Dimitar Nikolov, Urban Ingelsson, Virendra Singh and Erik Larsson, "Estimating error-probability and its application for optimizing Roll-back Recovery with Checkpointing", 5th IEEE International Symposium on Electronic Design, Test & Applications (DELTA 2010), Ho Chi Minh City, Vietnam, January 13-15, 2010.

Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman, "Parallel X-Fault Simulation with Critical Path Tracing Technique", Proceedings of the IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany, 8 - 12 March, 2010.

Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman, "Structural Fault Collapsing by Superposition of BDDs for Test Generation in Digital Circuits",  Proceedings of the International Symposium on Quality Electronic Design (ISQED), San Jose, USA, March 22-24, 2010.

Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, "Constraint-based Test Pattern Generation at the Register-Transfer Level", The IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2010), Vienna, April 14-16, 2010.

Andre Sülflow, Görschwin Fey, Rolf Drechsler, "Using QBF to increase accuracy of SAT-based debugging", The IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, 30 May - 2 June, 2010.

R.Ubar, D.Mironov, J.Raik, A.Jutman, "Fault Collapsing with Linear Complexity in Digital Circuits", The IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, 30 May - 2 June, 2010.

Roderick Bloem, Alessandro Cimatti, Karin Greimel, Georg Hofferek, Robert Könighofer, Marco Roveri, Viktor Schuppan, Richard Seeber, "RATSY - A new Requirements Analysis Tool with Synthesis", 22nd International Conference on Computer Aided Verification (CAV 2010), Edinburgh, UK, July 15-19, 2010.

Dimitar Nikolov, Erik Karlsson, Urban Ingelsson, Virendra Signh, and Erik Larsson, Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC, The 10th Swedish System-on-Chip Conference (SSoCC), Kolmården, Sweden, May 2010.

Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson, and Erik Larsson, "Efficient Embedding of Deterministic Test Data", The 10th Swedish System-on-Chip Conference (SSoCC), Kolmården, Sweden, May 2010.

Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson, "Test Time Analysis for IEEE P1687", IEEE 19th Asian Test Symposium (ATS 2010), Shanghai, China, December 2010.

Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson and Erik Larsson, "Efficient embedding of deterministic test data", IEEE 19th Asian Test Symposium (ATS 2010), Shanghai, China, December 2010.

Dimitar Nikolov, Mikael Väyrynen, Urban Ingelsson, Erik Larsson, and Virendra Singh, "Optimizing Fault Tolerance for Multi-Processor System-on-Chip", Design and Test Technology for Dependable Systems-on-chip, Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus (Eds.), 2010, Hardcover, ISBN: 978-1-6096-0212-3.

Robert Könighofer, Georg Hofferek, Roderick Bloem: "Debugging Unrealizable Specifications with Model-Based Diagnosis", Haifa Verification Conference 2010, October 05-07, 2010, Haifa, Israel.

Jaan Raik, Urmas Repinski, Raimund Ubar, Maksim Jenihhin, Anton Chepurov, "High-Level Design Error Diagnosis Using Backtrace on Decision Diagrams", 28th Norchip Conference, 15-16 November 2010, Tampere, Finland.

Jaan Raik, Urmas Repinski, Maksim Jenihhin, Anton Chepurov, "High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis", Design and Test Technology for Dependable Systems-on-chip, Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus (Eds.), 2010, Hardcover, ISBN: 978-1-6096-0212-3.

Sergei Kostin, Raimund Ubar, Jaan Raik, "Macro Level Defect-Oriented Diagnosability of Digital Circuits", 12th Biennial Baltic Electronics Conference (BEC 2010), October 4-6, 2010, Tallinn, Estonia.

Uljana Reinsalu, Jaan Raik, Raimund Ubar, "Register-Transfer Level Deductive Fault Simulation Using Decision Diagrams", 12th Biennial Baltic Electronics Conference (BEC 2010), October 4-6, 2010, Tallinn, Estonia.

Görschwin Fey, André Sülflow, Rolf Drechsler, "Towards Unifying Localization and Explanation for Automated Debugging", International Workshop on Microprocessor Test and Verification (MTV), Austin, Texas, 2010 

Alexander Finder, Görschwin Fey, "Evaluating Debugging Algorithms from a Qualitative Perspective", Forum on specification & Design Languages (FDL), Southampton, 2010 

Andre Sülflow, Rolf Drechsler, "Automatic Fault Localization for Programmable Logic Controllers", Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT), Braunschweig, 2010

A. Tsertov, A. Jutman, S. Devadze, "Testing Beyond the SoCs in a Lego Style". In Proc. of IEEE East-West Design & Test Symposium (EWDTS’10)St. Petersburg, Russia, Sept. 17-20, 2010, pp. 334 - 338 

Publications 2011

Georg Hofferek, Roderick Bloem - "Controller Synthesis for Pipelined Circuits Using Uninterpreted Functions" - Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MemoCODE 2011)

Robert Könighofer, Roderick Bloem - "Automated Error Localization and Correction for Imperative Programs" - Proceedings of 11th International Conference 2011 Formal Methods in Computer Aided Design (FMCAD 2011)

Matthias Schlaipfer, Georg Hofferek, Roderick Bloem - "Generalized Reactivity(1) Synthesis without a Monolithic Strategy" - Haifa Verification Conference 2011 (HVC'11), Dec 06-08 2011, Haifa, Israel

Robert Könighofer, Georg Hofferek, Roderick Bloem - Debugging formal specifications: a practical approach using model-based diagnosis and counterstrategies. - International journal on software tools for technology transfer (STTT), 2011.

Alexander Finder, André Sülflow, Görschwin Fey, "Latency Analysis for Sequential Circuits", GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TUZ), Passau, 2011

Raik, J; Rannaste, A; Jenihhin, M; Viilukas, T; Fujiwara, H; Ubar, R (2011). Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. Proceedings of IEEE European Test Symposium, (1 - 6).IEEE Computer Society Press 3.1.

Ubar, Raimund; Raik, Jaan; Jutman, Artur; Jenihhin, Maksim (2011). Diagnostic Modeling of Digital Systems with Multi-Level Decision Diagrams. Design and Test Technology for Dependable Systems-on-chip (92 - 118). USA, Hershey - New York: IGI Publishing

Reinsalu, Uljana; Raik, Jaan; Ubar, Raimund; Ellervee, Peeter (2011). Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. Proceedings of 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (1 - 6). Vancouver, Canada: IEEE Computer Society

Guarnieri, V; Hantson, H; Raik, J; Jenihhin, M; Bombieri, N; Pravadelli, G; Fummi, F; Ubar, R (2011). Mutation Analysis for SystemC Designs at TLM. 12th IEEE Latin-American Test Workshop Proceedings (1 - 6). Porto de Galinhas, Brasiilia: IEEE Computer Society Press

Karputkin, Anton; Ubar, Raimund; Tombak, Mati; Raik, Jaan (2011). Probabilistic Equivalence Checking Based on High-Level Decision Diagrams. 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 13-15, 2011, Cottbus, Germany. IEEE Computer Society Press, 2011, 423 - 428.

Karputkin, Anton; Ubar, Raimund; Tombak, Mati; Raik, Jaan (2011). Automated Correction of Design Errors by Edge Redirection on High-Level Decision Diagrams. IEEE International High Level Design Validation and Test Workshop, Napa Valley, Nov. 9-11, 2011. IEEE Computer Society, 2011.

Raik, Jaan; Repinski, Urmas; Jenihhin, Maksim; Chepurov, Anton (2011). High-Level Decision Diagram Simulation for Diagnosis and Soft-Error Analysis. Design and Test Technology for Dependable Systems-on-Chip (294 - 309).IGI Publishing

Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson. Access Time Analysis for IEEE P1687, IEEE Transactions on Computers, 2011.

Farrokh Ghani Zadegan, Urban Ingelsson, Golnaz Asani, Gunnar Carlsson, Erik Larsson. Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints, 20th IEEE Asian Test Symposium (ATS11), New Delhi, India, November 21-23, 2011.

Golnaz Asani, Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson. Test Scheduling with Constraints for IEEE P1687, International Test Conference (ITC11), Anaheim, CA, USA, September 18-23, 2011.

Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson. Automated Design for IEEE P1687, The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011.

Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson. Level of Confidence Study for Roll-back Recovery with Checkpointing, The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011.

Urban Ingelsson, Shih-Yen Chang, Erik Larsson. Cost Reduction of Wear-Out Monitoring by Measurement Point Selection, The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011.

Gunnar Carlsson, Artur Jutman, Erik Larsson. SoC-Level Fault Management based on P1687 IJTAG, Design, Automation and Test in Europe (DATE 2011), Grenoble, France, March 14-18, 2011.

Urban Ingelsson, Shih-Yen Chang, Erik Larsson. Measurement Point Selection for In-Operation Wear-Out Monitoring, 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011.

Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson. Design Automation for IEEE P1687, Design, Automation and Test in Europe (DATE 2011), Grenoble, France, March 14-18, 2011.

A. Tsertov, R. Ubar, A. Jutman, S. Devadze, “SoC and Board Modeling for Processor-Centric Board Testing”, in Proc. of 14th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD’2011), Oulu, Finland, Aug 31-Sept 2, 2011, pp. 575-582.

A. Jutman, I. Aleksejev, S. Devadze, “FPGA-Enabled Embedded Instrumentation Platform”, in Industrial Track of 16th IEEE European Test Symposium (ETS’2011), Trondheim, Norway, May 23-27, 2011.

A. Jutman, S. Devadze, J. Aleksejev, “System-Wide Fault Management based on IEEE P1687 IJTAG”, in Proc. of 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC’2011), Montpellier, France, June 20-22, 2011.

A. Tsertov, R. Ubar, A. Jutman, S. Devadze, “Automatic SoC Level Test Path Synthesis Based on Partial Functional Models”, in Proc. of IEEE 20th Asian Test Symposium (ATS’2011), New Delhi, India, Nov. 21-23, 2011, pp. 532-538.

Publications 2012

Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson, Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687, EDA Industry Standards issue of IEEE Design & Test Magazine, ISSN: 0740-7475, Digital Object Identifier: 10.1109/MDT.2012.2182984, Mar/Apr 2012

Alexander Finder, Görschwin Fey: "Evaluating Debugging Algorithms from a Qualitative Perspective", Book title: System Specification and Design Languages - Selected Contributions from FDL 2010, Tom J. Kazmierski and Adam Morawiec (Eds.), Springer, 2012, ISBN:978-1-4614-1426-1, pp. 21-36.

T.Viilukas, A.Karputkin, J.Raik, M.Jenihhin, R.Ubar, H.Fujiwara, Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. Journal of Electronic Testing: Theory and Applications, Springer, vol. 28, no. 4, pp. 511 – 521, 2012. DOI 10.1007/s10836-012-5312-5

V. Guarnieri, G. Di Guglielmo, N. Bombieri, G. Pravadelli, F. Fummi, H. Hantson, J.Raik, M. Jenihhin, R.Ubar, On the Reuse of TLM Mutation Analysis at RTL. Journal of Electronic Testing-Theory and Applications, Journal of Electronic Testing: Theory and Applications, Springer, vol. 28, no. 4, 2012. DOI 10.1007/s10836-012-5303-6

Shibin, Konstantin; Devadze, Sergei; Rosin, Vjatseslav; Jutman, Artur; Ubar, Raimund (2012). Open-Source JTAG Simulator Bundle for Labs. International Journal of Electronics and Telecommunications, 58(3), 233 - 239, DOI: 10.2478/v10177-012-0032-4.

R. Bloem, R. Drechsler, G. Fey, A. Finder, G. Hofferek, R. Koenighofer, J. Raik, U. Repinski, A. Suelflow, FoREnSiC - An Automatic Debugging Environment for C Programs. Haifa Verification Conference, IBM Research Labs, Haifa, Israel.

Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler: "Complete and Effective Robustness Checking by Means of Interpolation", Formal Methods in Computer-Aided Design (FMCAD), Cambridge, UK, 2012, pp. 82-90.

Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson, Re-using Chip Level DFT at Board Level, 17th IEEE European Test Symposium (ETS), France, May 2012.

Kim Petersen, Dimitar Nikolov, Urban Ingelsson, Gunnar Carlsson, Erik Larsson, An MPSoCs demonstrator for fault injection and fault handling in an IEEE P1687 environment, IEEE European Test Symposium (ETS), Annecy, France, May 2012.

E. Larsson, K. Shibin, Fault management in an IEEE P1687 (IJTAG) environment, IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Tallinn, Estonia, pp. 7-7, 2012-04-18.

E. Larsson, F. Ghani Zadegan: Accessing Embedded DfT Instruments with IEEE P1687, Asian Test Symposium, Niigata, Japan, pp. 71-76, 2012-11-20.

Ehlers, R.; Könighofer, R.; Hofferek, G.: Symbolically Synthesizing Small Circuits. - in: Proceedings of the 12th Conference on Formal Methods in Computer-Aided Design (FMCAD 2012), pages 91 - 100.

Bloem, R. P.; Gamauf , H.-J.; Hofferek, G.; Könighofer, B.; Könighofer, R.: Synthesizing Robust Systems with RATSY. - in: Proceedings First Workshop on Synthesis (SYNT 2012), pages 47 - 53.

Könighofer, R.; Bloem, R. P.: Repair with On-The-Fly Program Analysis. - in: Haifa Verification Conference (HVC 2012); 2012.

J. Raik, U. Repinski, H. Hantson, M. Jenihhin, G. Di Guglielmo, G. Pravadelli, F. Fummi, Combining Dynamic Slicing and Mutation Operators for ESL Correction. IEEE European Test Symposium, IEEE Computer Society Press.

J. Raik, U. Repinski, Comparison of Model-Based Error Localization Algorithms for C Designs. Proc. of 10th East-West Design & Test Symposium, Kharkov, Ukraine, September 14-17, 2012.

H. Hantson, U. Repinski, J. Raik, M. Jenihhin, R. Ubar, Diagnosis and Correction of Multiple Design Errors Using Critical Path Tracing and Mutation Analysis. 13th IEEE Latin-American Test Workshop Proceedings, pp. 27 – 32.

J. Raik, V. Govind, Low-Area Boundary BIST Architecture for Mesh-like Network-on-Chip. IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 95 – 100.

M. Jenihhin, S. Baranov, J. Raik, V. Tihhomirov, PSL Assertion Checkers Synthesis with ASM Based HLS Tool ABELITE, 13th IEEE Latin-American Test Workshop Proceedings, pp. 131 – 136.

A. Karputkin, R. Ubar, M. Tombak, J. Raik, Automated Correction of Design Errors by Edge Redirection on High-Level Decision Diagrams. 13th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, pp. 686 - 693.

J. Raik, T. Drenkhan, M. Jenihhin, T. Viilukas, A. Karputkin, A. Tšepurov, R. Ubar, Generating Directed Tests for C Programs using RTL ATPG. Proceedings of the IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12), Niigata, Japan, November 22-23, 2012.

R. Ubar, S. Kostin, J. Raik, How to Prove that a Circuit is Fault-Free? Proc. EUROMICRO, Cesme, Turkey, Sept. 5-8, 2012.

A. Tšepurov, V. Tihhomirov, M. Jenihhin, J. Raik, G. Bartsch, J.-H. Meza Escobar, H.-D. Wuttke, Localization of Bugs in Processor Designs Using zamiaCAD Framework. 13th International Workshop on Microprocessor Test and Verification (MTV 2012) Common Challenges and Solutions, Austin, USA, December 10–12, 2012.

R. Ubar, J. Raik, S. Kostin, J. Kousaar, Multiple Fault Diagnosis with BDD based Boolean Differential Equations, Proc. of Baltic Electronics Conference, Tallinn, October 3-5, 2012.

R. Ubar, S. Kostin, J. Raik, Multiple Stuck-at-Fault Detection Theorem. 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 18-20, 2012, Tallinn, Estonia.

Jutman, Artur; Devadze, Sergei; Aleksejev, Igor; Wenzel, Thomas (2012). Embedded Synthetic Instruments for Board-Level Testing. IEEE 17th European Test Symposium, Annecy, France, May 28 – June 1. IEEE Computer Society, 2012.

Aleksejev, Igor; Jutman, Artur; Devadze, Sergei; Odintsov, Sergei; Wenzel, Thomas (2012). FPGA-Based Synthetic Instrumentation for Board Test. 43th IEEE International Test Conference, Anaheim, CA, USA, Nov 4-9, 2012. IEEE Computer Society, 2012, 1 - 6.

Publications 2013

Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin. Automated design error debug using high-level decision diagrams and mutation operators. Journal of Microprocessors and Microsystems, Elsevier, http://dx.doi.org/10.1016/j.micpro.2012.11.004 (In Press).

Khalimov, A.; Jacobs, S.; Bloem, R. P.: Towards Efficient Parameterized Synthesis. - in: Proceedings of 14th Conference on Verification, Model Checking, and Abstract Interpretation (VMCAI 2013), (In Press).