Motivation

Increasing design costs are the main challenge facing the semiconductor community. Assuring the correctness of the design contributes to the major part of the problem. While diagnosis and correction of errors are more time-consuming compared to error detection, they have received far less attention, both, in terms of research works and industrial tools introduced.

Another, orthogonal, threat to the development is the rapidly growing rate of soft errors in the emerging nanometer technologies. According to roadmaps, soft errors in sequential logic are becoming a more severe issue than in memories. However, the design community is not ready for this challenge because existing soft error escape identification methods for sequential logic are inadequate.

DIAMOND project contends the above-mentioned challenges by providing a systematic methodology and an integrated environment for the diagnosis and correction of errors on different abstraction levels and from different sources.